CAREER
Explore the opportunity of working with top-notch engineers who bring together world-class talent to shape the future of technology. You will get the chance to lead in advanced chip design, IP development, and high-performance engineering services—powering next-generation consumer electronics, automotive systems, AI-driven devices, and communication technologies. We foster a culture of innovation, creativity, and continuous learning, providing ana environment where talented engineers, developers, and professionals can grow and build meaningful, impactful careers.
You’ll collaborate with experts on high-impact projects and be part of a team that values integrity, ownership, teamwork, and long-term development.
FIND YOUR CAREER
R&D
FULL-TIME
JUNIOR LEVEL
To manage and optimize the design infrastructure and EDA (Electronic Design Automation) environment, serving as the bridge between foundry requirements and the IC design team. #AgileDevelopment #Linux_Environment #PDK_Management (Process Design Kits) Si-Vision is growing, and we are looking for a CAD Engineer to manage our design infrastructure and EDA environment. By joining us, you will work alongside and be mentored by world-class professional engineers. This is a unique opportunity to sharpen your technical expertise through hands-on experience with advanced methodologies and industry-leading tools.
Responsibilities- Learn how to extract and summarize vital and useful information from technical documents.
- Work closely with the design team throughout the design cycle to gather all the design requirements and layout constraints.
- Develop skills for cell-level IC layout using custom IC layout tools.
- Learn how to estimate block-level area and do floor plans while considering the appropriate layout effects.
- Learn how to implement block-level routing while monitoring interconnect parasitic, reliability, and manufacturability.
- On the block level, develop physical verification skills (LVS/DRC/Antenna/EMIR/PERC/PEX).
- Sign off on the final layout design (Block-level) while meeting all the requirements and quality metrics.
- Developing scripts using programming languages such as Tcl, Perl, and Shell is a plus.
- Apply the layout process effectively to ensure the application of layout design best practices.
- B.Sc in Electronics Engineering
- Linux & Windows
- Layout tools knowledge
- Scripting is a plus
R&D
FULL-TIME
JUNIOR LEVEL
An Analog Layout Designer works in a team to develop and verify high-quality layouts for analog mixed-signal ICs including RF circuits, high-speed interfaces, power management, and advanced data converters on deep sub-micron technologies such as CMOS, SOI, and FinFET.
Si-Vision is growing, and we are looking for a Junior Layout Engineer. You will be mentored by world-class engineers while gaining hands-on experience with advanced methodologies and tools.
Responsibilities- Extract and summarize vital information from technical documents.
- Work closely with design teams to gather layout constraints.
- Develop cell-level IC layouts using custom tools.
- Estimate block-level area and perform floor planning.
- Implement block-level routing while monitoring parasitics and reliability.
- Develop physical verification skills (LVS/DRC/Antenna/EMIR/PERC/PEX).
- Sign off final block-level layouts meeting quality metrics.
- Scripting using Tcl, Perl, or Shell is a plus.
- Apply layout best practices.
- B.Sc in Electronics Engineering.
- Awareness of IC layout flows and fabrication steps.
- Basic knowledge of analog circuit design.
- Understanding of layout methodologies (device matching, signal conditioning).
- Linux & Windows.
- Layout tools: Synopsys Custom Compiler / Cadence Virtuoso (plus).
- Verification tools: IC-Validator / Calibre / PVS (plus).
- Scripting (Tcl, Perl, Shell) is a plus.
- Presentation and time-management skills.
R&D
FULL-TIME
MID LEVEL
As a Mid-Level Layout Engineer, you will work on high-performance analog mixed-signal IC layouts, collaborating closely with design teams while handling block-level and chip-level responsibilities.
Responsibilities- Communicate effectively within the team and adapt to agile environments.
- Track timelines and report progress regularly.
- Document and present ideas clearly.
- Perform cell-level IC layout using custom tools.
- Estimate block-level area and floor plans.
- Implement routing with awareness of parasitics and manufacturability.
- Run physical verification (LVS/DRC/Antenna/EMIR/PERC/PEX).
- Sign off final layouts.
- Develop scripts (Tcl, Perl, Shell).
- Apply layout best practices and support full-chip verification.
- B.Sc in Electronics Engineering.
- 1+ years of experience.
- Strong understanding of IC layout flows.
- Analog design basics.
- Layout tools: Synopsys Custom Compiler, Cadence Virtuoso.
- Verification tools: IC-Validator, Calibre, PVS.
- Scripting: Tcl, Perl, Shell.
- Presentation and time-management skills.
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